For solder flip chip assembly of a first level package or device, the solder interconnects are formed by joining solder bumps on the chip with solder bumps on the substrate. The solder bumps on the substrate help compensate for chip bump height variations and substrate warpage. Flip chip technology allows the largest numbers of inputs/outputs (“I/Os”) for the smallest footprint of the chip. This enables manufacturing small packages known in the art as chip-scale packages.
IBM introduced this technology in the early 1960's with the solid logic technology in their IBM System/360™. It extended interconnection capabilities beyond existing wire-bonding techniques, allowing the area array solder-bump configuration to extend over the entire surface of the chip (die) providing solder bumps for interconnection to a substrate by the so-called “C4” method. This allowed for the highest possible I/O counts to meet the increasing demand for electrical functionality and reliability in IC technology. “C4” comprises the term for describing the method of connecting semiconductor and other devices, also known as the IBM “flip chip” or “controlled collapse chip connection,” from which the industry derives the acronym “C4.” The devices that employ C4 technology comprise integrated circuits (“IC” chips), passive filters, detector arrays and microelectromechanical systems (“MEMS”) all of which are well known in the art. The present invention comprises processes for manufacturing these devices, and the products obtained by these processes.
The C4 method interconnects devices to external circuitry by means of solder bumps that have been deposited on semiconductor chip pads or substrates. In order to mount the chip to external circuits such as a circuit board or another chip or a wafer used in manufacturing other chips, a chip having solder bumps is flipped over so that the solder is aligned with matching connecting sites (e.g., connector pads) on an external circuit, and the connection completed by raising the temperature of the solder so that it flows and adheres to the connecting sites.
The original wafer-bumping process of metal mask evaporation comprised the evaporation onto a wafer surface of solder through mask openings in an area array fashion. This wafer-bumping and the structure obtained are sometimes referred to as ball limiting metallurgy or under board metallization, under mask metallization, or under mask-bump metallurgy (“UBM”). In its broader aspect UBM comprises the application of a metal coating to the die contact pads such as aluminum or copper contact pads, where the metal coating provides a surface that can adhere to solder. The UBM typically consist of an adhesion layer, such as Ti or TiW, a barrier layer, such as Ni and a solder wettable layer, such as Cu or Au to which the solder gets attached.
The need for increased I/O density and count, and pressures to lower the cost of flip-chip interconnections have spurred the development of other wafer bumping techniques such as electroplating or stencil-printing/paste-screening (solder paste) bump processes. Some of the more newly developed bumping processes include transfer printing, solder jetting, and bumpless and conductive particle applications.
Other techniques used for the solder bumping process on the semiconductor substrates include, for example, screen printing of solder paste, ball mounting of preformed solder balls, injection molded solder and the like.
The overview of flip chip technology shows its major advantage lies in utilizing the total chip area to make the I/O connections, whereas wire bonding uses only the chip periphery.
For solder flip chip assembly at tight bump pitch in the first level packaging, the flip chip interconnects are formed by the connection between solder bumps on the chip side and solder bumps on the substrate side. The solder bumps on the substrates help compensate for die bump height variations and substrate warpage. In order to get stringent substrate bump co-planarity, a coining process is applied to form flat tops on the solder bumps.
The current manufacturing technology for forming solder bumps on organic substrates is the solder paste stencil printing method. The stencil printing method is a low cost simple process for forming solder bumps on substrates which have island type I/Os without having to employ a photo lithography process.
As an alternative to the bumps on the substrates, Tessera reported etched Cu post substrate technology that can potentially reduce the interconnection thermal resistance. Hongyu Ran et al, “Thermal characterization of copper contact interconnect for DRAM package stacking in memory-intensive consumer applications”, Advancing Microelectronics, Vol. 34, No. 6 (2007), pp. 10-14.
The Cu posts on the substrate enable a higher stand-off height between the chip and the substrate and better capability to carry higher current when the current flows from the substrate to the chip. The Cu posts on the substrate however do not include solder, so they need a sufficient volume of solder from the bumps on the chips to enable flip chip assembly. Even if the Cu-post substrates are used for flip chip packing with dies that have enough solder bumps, the increase of the Cu/solder ratio in the interconnects increases the stress transmitted to the Cu/ultra low k layers in the back-end-of-line (“BEOL”) structure and results in flip chip assembly failure.
Also, for reliability benefits on electromigration to improve current carrying capability when the current flows from the chip to the substrate, Cu pillar die bumps only or Cu pillar die bumps with small solder caps have been integrated as chip side bumps in high volume manufacturing.
Claims have been made that the integrated Cu die side bumps using a Cu electroplating process in high volume manufacturing provide reliability benefits with regard to stress, electromigration and thermal conductivity. Andrew Yeoh et al., “Copper die bumps (First Level Interconnect) and Low-K dielectrics in 65 nm high volume manufacturing”, Proceedings of 56th Electronic Components and Technology Conference, p. 1611, San Diego, Calif., May. 2006.
In the cases of Cu pillar die bumps only, or Cu pillar die bumps with small solder caps on the chip side, the Cu posts on the substrates cannot be used for flip chip packaging. The conventional flip chip assembly with Cu pillar die bumps only with Cu posts on the substrate is not possible because there is not any solder materials in the interconnect. Also, in the case of Cu pillar die bumps with small solder caps, the Cu/Sn ratio in a interconnect is too high.
Accordingly, it is generally desirable to have a new packaging paradigm for flip chips with high current capability in both directions of the solder joint, that is, from the chip to the substrate and from the substrate to the chip, along with less stress transmitted to the BEOL structure in order to increase the reliability of electronic products, i.e. the aforementioned devices.